Computer Organization And Architecture MCQ PART - 9

Computer Architecture MCQ Questions

1. which of the following is interrupt mode:

    a. Task mode

    b. Executive mode

    c. Both a & b

    d. None of these

2. Mode of addresses in control memory are:

    a. Executive mode

    b. Task mode

    c. Both a & b

    d. None of these

3. Addresses in control memory is made by __________ for each register group:

    a. Address select logic

    b. Data select logic

    c. Control select logic

    d. All of these

4. There are how many register groups in control memory:

    a. 3

    b. 5

    c. 6

    d. 8

5. What type of circuit is used by control memory to interconnect registers:

    a. Data routing circuit

    b. Address routing circuit

    c. Control routing circuit

    d. None of the these

6. Which memory is used to copy instructions or data currently used by CPU:

    a. Main memory

    b. Secondary memory

    c. Cache memory

    d. None of these

7. Copy of instruction in cache memory is known as:

    a. Execution cache

    b. Data cache

    c. Instruction cache

    d. All of these

8. Copy of data in cache memory is called:

    a. Data cache

    b. Execution cache

    c. Address cache

    d. Control cache

9. What are 2 advantages of cache memory:

    a. Reduction of average access time for CPU memory

    b. Reduction of bandwidth of available memory of CPU

    c. Both a & b

    d. None of these

10. On what method search in cache memory used by the system:

    a. Cache directing

    b. Cache mapping

    c. Cache controlling

    d. Cache invalidation

11. ______ process starts when a cpu with cache refers to a memory:

    a. Main memory

    b. External memory

    c. Cache

    d. All of these

12. When cache process starts hit and miss rate defines in cache directory:

    a. during search reads

    b. during search writes

    c. during replace writes

    d. during finding writes

13. In cache memory hit rate indicates:

    a. Data from requested address is not available

    b. Data from requested address is available

    c. Control from requested address is available

    d. Address from   requested address is not available

14. In cache memory miss rate indicates:

    a. Availability of requested data

    b. Availability of requested address

    c. Non-Availability of requested data

    d. Non-Availability of requested address

15. Which 3 areas are used by cache process:

    a. Search, updating, invalidation

    b. Write, updating, invalidation

    c. Search, read, updating

    d. Invalidation, updating, requesting

16. Updating writes to cache data and also to _________:

    a. Directories

    b. Memory

    c. Registers

    d. Folders

17. Invalidation   writes  only  to _________ erases previously residing address in memory:

    a. Folders

    b. Memory

    c. Directory

    d. Files

18. __________ machine instruction creates branching to some specified location in main memory if result of last ALU operation is Zero or Zero flag is set:

    a. Branch on One

    b. Branch on Three

    c. Branch on Nine

    d. Branch on Zero

19. Full form of CAR:

    a. Control address register

    b. Content address register

    c. Condition accumulator resource

    d. Code address register

20. Two types of microinstructions are:

    a. Branching

    b. Non-branching

    c. Both a & b

    d. None of these

21. Which are 3 ways to determine address of next micro instruction to be executed:

    a. Next sequential address

    b. Branching

    c. Interrupt testing

    d. All of these

22. Branching can be ____________ :

    a. Conditional

    b. Unconditional

    c.  Both a & b

    d. None of these

23. In which branching condition is tested which is determined by status bit of ALU:

    a. Unconditional

    b. Conditional

    c. Both a & b

    d. None of these

24. which branch is achieved by fixing status bit that output of multiplexer is always one:

    a. Unconditional

    b. Conditional

    c. Looping

    d. All of these

25. Which register is used to store addresses of control memory from where instruction is fetched:

    a. MAR

    b. BAR

    c. CAR

    d. DAR

26. Control ROM is the control memory that holds:

    a. Control words

    b. Memory words

    c. Multiplexers

    d. Decoders

27. Opcode is the machine instruction obtained from decoding instruction stored in:

    a. Stack pointer

    b. Address pointer

    c. Instruction register

    d. Incrementer

28. Branch logic determines which should be adopted to select the _________ next  value among possibilities:

    a. CAR

    b. GAR

    c. HAR

    d. TAR

29. _________ generates CAR+1 as possibility of next CAR value:

    a. Decrementer

    b. Incrementer

    c. Postfix

    d. Prefix

30. __________ used to hold return address for operations of subroutine call branch:

    a. TBR

    b. HDR

    c. SDR

    d. SBR

31. Which of following 2 types of computer system considered by micro programmed unit:

    a. Micro level computers

    b. Machine level computers

    c. Both a & b

    d. None of these

32. Following are the components of micro programmed control unit:

    a. Subroutine register

    b. Control address register

    c. Memory Of 128 words with 20 bits per words

    d. All of these

33. Various machine level components are:

    a. Address register  

    b. Program counter

    c. Data register

    d. Accumulator register

    e. Memory of 2K,16 bits/word RAM

    f. Multiplexers

    g. All of these

34. Data transfers are done using:

    a. Multiplexer switching

    b. Demultiplexer switching

    c. Adder switching

    d. Subtractor switching

35. PC can be loaded from ____________ :

    a. BR

    b. CR

    c. AR

    d. TR

 PART - 10

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