Computer Architecture And Organization MCQ
1. Which functions are performed by CU:
a. Data exchange b/w CPU and memory or I/O modules
b. External operations
c. Internal operations inside CPU
d.
Both a & c
2. Which are internal operations inside
CPU:
a. Data transfer b/w registers
b. Instructing ALU to operate data
c. Regulation of other internal operations
d.
All of these
3. How many paths taken by movement of
data in CU:
a. 3
b. 4
c. 5
d.
2
4. 2 data paths in CU are:
a. Internal data paths
b. External data paths
c.
Both a & b
d. None of these
5. ___________ is the data paths link CPU
registers with memory or I/O modules:
a.
External data paths
b. Internal data paths
c. Boreal data paths
d. Exchange data paths
6. ____________ is data paths there is
movement of data from one register to another or b/w ALU and a register:
a. External
b. Boreal
c.
Internal
d. Exchange
7. Which is the input of control unit:
a. Master clock signal
b. Instruction register
c. Flags
d. Control signals from bus
e.
All of these
8. If __________ flag is set then control unit issues control signals that causes program counter to be incremented by 1:
a.
Zero
b. One
c. Three
d. Eight
9. Which control unit is implemented as
combinational circuit in the hardware:
a. Microprogrammed control unit
b.
Hardwired control unit
c. Blockprogrammed control unit
d. Macroprogrammed control unit
10. Microprograms are usually stored in:
a.
ROM
b. RAM
c. SAM
d. SAN
11. Among them which is the faster control
unit:
a.
Hardwired
b. Microprogrammed
c. Both a & b
d. None of these
12. For CISC architecture ___________
controllers are better:
a.
Microprogrammed
b. Hardwired
c. Betterwired
d. None of these
13. Full form of FSM is:
a.
Finite state machine
b. Fix state machine
c. Fun source metal
d. All of these
14. Rules of FSM are encoded in:
a. ROM
b. Random logic
c. Programmable logic array
d.
All of these
15. In RISC architecture access to
registers is made as a block and register file in a particular register can be
selected by using:
a. Multiplexer
b.
Decoder
c. Subtractor
d. Adder
16. Outputs of instruction/data path in CU
are:
a. Reg R/W
b.
Load/Reg-Reg
c. ALU function select
d.
Load control
e. Read control
f.
IR Latch
g.
JUMP/Branch/Next PC
h.
All of these
17. One last bit of control output is for
control of state:
a. Minor
b.
Major
c. Mixer
d. None of these
18. Following are 4 major states for
‘load’ are:
a. Fetch
b. Decode
c. Memory
d. Write back
e.
All of these
19. Jump has 3 major states are:
a. Fetch
b. Decode
c. Complete
d.
All of these
20. __________ state keeps track of
position related to execution of an instruction:
a. Major
b. Minor
c. Both a & b
d. None of these
21. An instruction always starts with
state ___________ :
a. 1
b. 2
c. 3
d.
0
22 Decoding of an instruction in RISC
architecture means decision on working of control unit for:
a.
Remainder of instructions
b. Divisor of instructions
c. Dividend of instructions
d. None
23. Which control is used during starting
of instruction cycle:
a. Write
b.
Read
c. R/W
d. None of these
24. ___________ function select takes op
code in IR translating to function of ALU and it may be compact binary code or
one line per ALU:
a.
ALU
b. CPU
c. Memory
d. Cache
25. __________ is dependent on instruction
type in CU:
a. Jump
b. Branch
c. NextPC
d.
All of these
26. __________ dependent on instruction
and major state and also comes in starting of data fetch state as well as write
back stage in CU:
a. Register read
b. Register write
c.
Register R/W
d. All of these
27. __________ dependence over op-code in C:
a. Load register
b.
Load Reg/Reg
c. Only Load
d. None of these
28. Full form of PLA in CU:
a.
Progrmmable Logic Array
b. Programs Load Array
c. Programmable Logic Accumulator
d. all of these
29. Which are tasks for execution of CU or
MCU:
a. Microinstruction execution
b. Microinstruction sequencing
c.
Both a & b
d. None of these
30. Branching is implemented by depending
on output of:
a.
CD
b. RG
c. CC
d. CR
31. Who determine under what conditions
the branching will occur and when:
a. By combination of CD and BT
b.
By combination of CD and BR
c. By combination of CD and CR
d. By combination of TD and BR
32. The character U is used to indicate:
a. Undefined transfers
b. Unfair transfers
c.
Unconditional transfers
d. All of these
33. Which field is used to requests for
branching:
a. DR
b. CR
c. TR
d.
BR
34. which field is used to determine what
type of transfer occurs:
a.
CR
b. SR
c. BR
d. MR
34. Source statements consist of 5fields
in microinstruction source code are:
a. Lable
b. Micro-ops
c. CD-spec
d. BR-spec
e. Address
f. All of these
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