Computer System Architecture MCQ With Answers
1. As the instruction length increases ------------ of instruction
addresses in all the instruction is ------------:
a. Implicit inclusion
b. Implicit and disadvantageous
c. Explicit and disadvantageous
d. Explicit and disadvantageous
2.
__________ is the sequence of operations performed by CPU in processing
an instruction:
a. Execute cycle
b. Fetch cycle
c. Decode
d. Instruction cycle
3. The time required to complete one
instruction is called:
a. Fetch time
b. Execution time
c. Control time
d. All of these
4. _______ is the step during which a new
instruction is read from the memory:
a. Decode
b. Fetch
c. Execute
d. None of these
5. _______ is the step during which the
operations specified by the instruction are executed:
a. Execute
b. Decode
c. Both a& b
d. None of these
6. Which code used to represent numbers,
letters, punctuation marks as well as control characters:
a. ASCII
b. EBCDIC
c. Both
d. None of these
7. abbreviation EBCDIC stand for:
a. Extended binary coded decimal
interchange code
b. External binary coded decimal
interchange code
c. Extra binary coded decimal interchange
code
d.
None of these
8. How many bit of EBCDIC code:
a. 7
b. 8
c. 5
d. 9
9. Which code the decimal digits are
represented by the 8421 BCD code preceded by 1111:
a. ASCII
b. EBCDIC
c. Both
d. None of these
10. ______ has the property that corrupting
or garbling a code word will likely produce a bit string that is not a code
word:
a. Error deleting codes
b. Error detecting codes
c. Error string codes
d. None of these
11. The
bit position in a _______ numbered from 1 through 2i-1:
a. Hamming code word
b. Hamming distance word
c. Both
d. None of these
12. Each check bit is grouped with the
information bits as specified by a _______:
a. Parity check code
b. Parity check matrix
c. Parity check bit
d. All of these
13. The pattern of groups that have odd
parity called the _______ must match one of the of columns in the parity check
matrix:
a. Syndrome
b. Dynodes
c. Both
d. None of these
14. Which are designed to interpret a
specified number of instruction code:
a. Programmer
b. Processors
c. Instruction
d. Opcode
15. Which code is a string of binary
digits:
a. Op code
b. Instruction code
c. Parity code
d. Operand code
16. Which instruction are used in
multithreaded parallel processor architecture:
a. Memory reference instruction
b. Memory reference format
c. Both
d. None of these
17. Which instruction are arranged as per
the protocols of memory reference format of the input file in a simple ASCII
sequence of integers between the range 0 to 99 separated by spaces without
formatted text and symbols:
a. Memory reference instruction
b. Memory reference format
c. Both
d. None of these
18. _________ is an external hardware event
which causes the CPU to interrupt the current instruction sequence:
a. Input interrupt
b. Output interrupt
c. Both
d. None of these
19. ISR stand for:
a. Interrupt save routine
b. Interrupt service routine
c. Input stages routine
d. All of these
20. Which interrupt services save all the
register and flags:
a. Save interrupt
b. Input/output interrupt
c. Service interrupt
d. All of these
21. Information is handled in the computer
by _________ :
a. Electrical digit
b. Electrical component
c. Electronic bit
d. None of these
22. 0 and 1 are know as ________ :
a. Byte
b. Bit
c. Digits
d. Component
23. 0 and 1 abbreviation for:
a. Binary digit
b. Octal digit
c. Both
d. None of these
24. How many bit of nibble group:
a. 5
b. 4
c. 7
d. 8
25. How many bit of bytes:
a. 3
b. 4
c. 6
d. 8
- Computer Organization And Architecture MCQ
- Advanced Computer Architecture MCQ Questions And Answers
- Computer Architecture MCQ
- Computer System Architecture MCQ
- Computer Architecture And Organization MCQ
